This invention relates generally to cross coupled logic circuits. More particularly, it describes a dual level differential current switch logic in a GaAs MESFET technology which uses cross-coupled buffer stages to improve noise margins while maintaining high speed operation.
In bipolar technology, differential current switch (DCS) logic offers speed and power advantages, particularly for certain logic functions such as level sensitive latches, exclusive-OR functions, or multiplexers. However, in GaAs technology, it is difficult to design a DCS logic family due to the relative lack of control of the threshold voltages of the FETs and the less sharply defined switching of the differential pair compared to silicon bipolar logic.
Although DCS logic circuits are very efficient for certain types of important logic functions, e.g., latches, exclusive-OR, multiplexers, they are not efficient at implementing other functions such as multiple input ANDs, or multiple input NORs. In contrast, other GaAs logic families, especially super buffer logic (SBL) or source follower logic (SFFL), are very good at multiple input NORs and AND-OR circuits, but do not lend themselves to implementing latches.
It would be desirable, when designing GaAs logic circuits, to combine DCS latches, exclusive-ORs, multiplexers, etc. with SBL or SFFL multiple input ANDs and NORs. Unfortunately, known GaAs DCS circuits do not interface easily with other logic families due to differences in logic levels and power supply voltages. One known DCS circuit is described in IEEE Electron Device Letters, Vol. EDL-7, No. 1, January 1986, at pages 47-48. This divide by four circuit obtains the performance of current switch design in GaAs, however, it uses a different power supply (-3.4V or -2.3V) than are found in SBL or SFFL designs (1.5V) and it also uses different logic levels. Lowering the power supply of this DCS design to integrate it with an SBL of SFFL logic circuit would significantly decrease its noise margin. This noise margin problem could be improved by increasing the widths of the FETs, however, without changing the circuit topology, the circuit performance is compromised because of the additional capacitive loading of the larger gates.